Added Makefile.
authorethereal <ethereal@ethv.net>
Mon, 7 Apr 2014 00:49:59 +0000 (18:49 -0600)
committerethereal <ethereal@ethv.net>
Mon, 7 Apr 2014 00:49:59 +0000 (18:49 -0600)
Makefile [new file with mode: 0644]
src/workshops/osdev/notes/notes-0.md
src/workshops/osdev/notes/notes-1.md
src/workshops/osdev/notes/notes-5.md

diff --git a/Makefile b/Makefile
new file mode 100644 (file)
index 0000000..e2c620c
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,8 @@
+.PHONY: all clean
+
+all:
+       mkdir -p gen/img/gen
+       ./update.py
+
+clean:
+       rm -rf gen
index f80bd6d..e7c80e9 100644 (file)
@@ -12,6 +12,8 @@ various useful stuff.
 
 ### Intel CPU model ###
 
+First, some notes on the general structure of the Intel CPU model.
+
 #### General-purpose registers ####
 
 x86_64-compatible CPUs have 16 64-bit general-purpose registers, in addition to
index a954b68..108e16c 100644 (file)
@@ -19,10 +19,6 @@ Topics:
 * Boot procedure
     * Bootloaders
     * Multiboot
-* Bare-bones kernel
-    * Write "Hello, World!" message to video RAM
-    * Assembling
-    * Executing
 * Virtual/physical memory
     * x86_64 paging structures
     * TLB (?)
index 9f76ed3..66d6e52 100644 (file)
     * SIPI
     * Delaying
     * Initial code
+    * x86_64 processor modes (revisited)
+* Per-CPU storage
+    * `swapgs`
 * ATA
 * ATA PIO/DMA
 * ATA PIO details:
     * IDENTIFY
-    * LBA (28- and 48-bit)
+    * LBA (28/48-bit)
     * READ SECTOR
     * WRITE SECTOR
+    * Software resets
 * To work on:
-    * SMP initialization code, get multiple processors working
+    * SMP initialization code, get multiple processors working (using provided
+        SMP AP init code)
     * Simple ATA PIO wrapper; assume presence of primary master and PIO ports
         at default locations